BL7448SM intelligent 8k-bit eeprom http://www.belling.com.cn - 1 - 8/16/2006 total 7 pages description BL7448SM is an ic card chip (module) made by 0.35um cmos eerpom process. it has 1024 byte eeprom with logical encryption and function. figure 1 features 1024 x 8 bit eeprom organization byte-wise addressing irreversible byte-wise write protection of every by te 1024 x1 bit organization of protection memory serial three-wire link end of processing indicated at data output minimum of 100,000 write/erase cycles data retention time :>10 years contacts configuration and serial interface accordi ng to iso 7816 standard (synchronous transmission) data can only be changed after entry of the correct 2-byte programmable security code pin description pin no. parameter symbol function description 1 c1 v dd supply voltage 2 c2 rst reset signal 3 c3 clk clock input 4 c4 n.c. not connected 5 c5 gnd ground 6 c6 nc not connected 7 c7 i/o bidirectional data line (open drain) 8 c8 nc not connected
BL7448SM intelligent 8k-bit eeprom http://www.belling.com.cn - 2 - 8/16/2006 total 7 pages function description block diagram figure 2 the BL7448SM consists of 1024 x 8 bit eeprom main memory and a 1024-bit protection- memory with prom functionality .the main memory can be irr eversibly protected against data change by writing the corresponding bit in the protection memory. once wr itten the protection bit cannot be erased. the main memory is erased and written byte by byte. normall y a data change consists of an erase and write procedure. it depends on the contents of the data b yte in the main memory and the new data byte whethe r the eeprom is really erased and/or written. if none of the 8 bits in the addressed byte requires a zer o-to- one transition the erase access will be suppressed. vice versa the write access will be suppressed if no one- to-zero transition is necessary. additionally to the above functions the BL7448SM pr ovides a security code logic, which controls the write/erase access to the memory. for this purpose, the BL7448SM contains a 3- byte security memory with an error counter ec and 2 bytes reference data. these 2 bytes as a whole are called programmable security code (psc). after power on the whole memory, except for the reference data, the memory can only be read . (the value of psc is 00)writing and erasing is only possible after a successful compari son of verification data with the internal reference data.
BL7448SM intelligent 8k-bit eeprom http://www.belling.com.cn - 3 - 8/16/2006 total 7 pages after eight successive unsuccessful comparisons the error counter blocks any subsequent attempt, and hence any possibility to write and era se. reset and answer-to-reset *reset after connecting the operating voltage to vcc, the chip will hold and wait the operation of reset. the operation of reset begins with rst from l to h, an d ends with clk from l to h. during the operation of reset, all commands will be ignored. after power on reset, the operation of reading mus t be execute before data can be altered. . *answer-to-reset answer-to-reset set the address counter to zero and output the first data. the other data can be read with clk signal. command rst rst i/o 1 command input 0 data output command byte1 byte2 address byte3 data operation mode s0 s1 s2 s3 s4 s5 a8 a9 a0~a7 d0~d7 1 0 0 0 1 1 data updata main memory & protection memory processing 1 1 0 0 1 1 data updata main memory processing 0 0 0 0 1 1 comp. data write protection memory processing 0 0 1 1 0 0 no effect read main memory & protection memory data output 0 1 1 1 0 0 no effect read main memory data outpu t v cc rst clk i/o 1 2 3 31 32 1 2 3 31 32 rst clk i/o t d4 t d4 t d2 t h t l t d5 ic sets i/o to state h figure 3 reset and answer-to-reset
BL7448SM intelligent 8k-bit eeprom http://www.belling.com.cn - 4 - 8/16/2006 total 7 pages figure 4 command input command mode write/erase operation write/erase, except for protection-memory note: write means from h to l, erase means from l t o h there are three kinds of write/erase operations: erase and write (the number of clock pulses=203, f requency <=20khz) write only: means the 8 bits in the addressed byte from h to l( the number of clock pulses =103, frequency <=20khz) erase only(=ff; the number of clock pulses =103, f requency <= 20khz) write/erase, include protection-memory as shipped, the protection-memory has been erased, it can be written only once. write protection-memory and compare data when comparison of the entered data byte is same as the assigned byte in the eeprom. the protection-memory is written. after sent a certain clk, the command of write/eras e will be over. after operation, the state of i/o p in will be changed from h to l. the i/o state can be changed when rst change from l to h. s0 s1 d6 d7 command input processing tw te 0 23 0 1 2 99 102 199 202 res clk e / w internal signal i/o figure 5 erase and write timing s0 s1 d6 d7 command input processing tw te 0 23 0 1 2 99 102 199 202 res clk e / w internal signal i/o figure 6 only write or erase read operation read main memory (see figure 7) this operation dont read the protection-memory. a fter 8 clk, the address of memory will be increased by additional pulse . 2 1 0 3 4 5 6 7 0 2 3 1 4 5 6 7 0 1 2 3 4 5 6 s0 s2 s3 s4 s5 s1 a8 a9 a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 bute 3 data bute 2 address bute 1 control byte
BL7448SM intelligent 8k-bit eeprom http://www.belling.com.cn - 5 - 8/16/2006 total 7 pages read main memory and protection-memory (see figure 8) after input this command, the next 8 clk will read out 8 bits data; the ninth clk will read out the content of protection-memory. after 9 clk, the addr ess of memory will be increased by additional pulse. security code verification byte1 byte2 address byte3 address operation mode 0 1 0 0 1 1 1 1 253 bit mask write error counter processing 1 0 1 1 0 0 1 1 254 psc byte1 verification 1 st psc byte processing 1 0 1 1 0 0 1 1 255 psc byte2 verification 2 nd psc byte processing command input data output rst clk a8 a9 d6 d7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 i/o 0 1 2 3 4 5 6 7 starting address random value starting address starting address + 1 starting address + n figure 7 read main memory 0 23 command input data output a8 a9 d6 d7 0 1 2 3 4 5 6 7 p0 0 1 2 3 4 5 6 7 p0 p0 0 1 2 3 4 5 6 7 p0 starting address starting address starting address +1 starting address + n random value rst clk i/o figure 8 read main memory and protection-memory security code verification user verification operation BL7448SM only can read when the security code verif ication is unsuccessful. the content of security co de cannot be read out. if you try to read security cod e, you only can get 00 the processing is: *write a bit of ec(the bit is not written before), the address of ec is 1021 *input the first byte of psc, the address is 1022 *input the second byte of psc, the address is 1023 *if the security verification is successful , the e c can be erased.
BL7448SM intelligent 8k-bit eeprom http://www.belling.com.cn - 6 - 8/16/2006 total 7 pages after security code identification , i/o will be ch anged from h to l. i/o will return to h when rst ch ange from l to h. ec cannot be erased automatically. write error counter (ec) before security code identification, only error cou nter (ec) can be written. a number of erased bit o f ec means what times ec can be written. after security code verification is successful, ec should be erase d before power off. after security code verification is unsuccessful, if it is verified again, ec must be written. input psc psc input start from lowest bit of low byte to high byte. if comparison of data is right, eeprom can b e written or erased before power-off and the correspo nding protection bit of psc is h, psc can be chan ged. write ec ec write enable compare 1st psc byte ok compare 2nd psc byte ok password verification ok,erase ec->ff yes yes yes no no no compare fobidden compare failed compare failed figure 9 verification procedure 0 23 command input data output a8 a9 d6 d7 0 1 2 3 4 5 6 7 p0 0 1 2 3 4 5 6 7 p0 p0 0 1 2 3 4 5 6 7 p0 starting address starting address starting address +1 starting address + n random value rst clk i/o figure 10. psc verification timing
BL7448SM intelligent 8k-bit eeprom http://www.belling.com.cn - 7 - 8/16/2006 total 7 pages electrical parameter absolute maximum ratings limit values parameter symbol min. typ. max unit supply voltage v cc -0.3 6.0 v input voltage (any pin) v i -0.3 6.0 v storage temperature t s -40 125 power comsumption pt 0 60 mw operation temperature ta -35 70 dc characteristics limit values parameter symbol min. typ. max unit supply voltage v cc 3.0 5.0 5.5 v supply current i cc 3 10 ma high-level input voltage (i/o,clk,rst) v ih 0.7v cc - v cc +0.3 v low-level input voltage (i/o,clk,rst) v il v gnd - 0.2 - 0.15v gnd v high-level input current (i/o,clk,rst) i h - - 50 ua low-level output current v ol =0.4v,open drain i ol 0.5 - - ma high-level leakage current v oh = v cc ,open drain i oh - - 50 a input capacitance c i - - 10 pf ac characteristics limit values parameter symbol min. typ. max unit clock frequency clk 20 khz clock high period t h 10 m s clock low period t l 10 m s setup time data t d1 4 m s delay time t d2 6 m s clock setup time for rst t d3 4 m s rst setup time for clock t d4 4 m s hold time data t d5 4 m s eraser time t er 5 ms write time t wr 5 ms
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